Tendencias industriales

After a challenging 2023, the global semiconductor industry is finally showing signs of recovery in the first half of 2024. As market demand rebounds, major wafer fabs are ramping up capital expenditures and expanding their capacities to prepare for a new growth peak.

On July 5, the source Moore's Law Is Dead revealed that AMD will release Zen 6 architecture chips in the second quarter of 2025, using TSMC's N3E process. Mass production will start before the end of 2025 at the earliest, but it is not ruled out that it may be postponed to 2026.

On July 1, according to foreign media reports, the United States has previously announced that it will impose new export controls on technologies such as EDA software necessary for designing GAAFET (all-gate field effect transistor) structure integrated circuits.

Cadence Electronics (USA) recently announced the expansion of its system IP portfolio with the addition of Cadence® Janus™ Network-on-Chip (NoC). As today's computing needs continue to increase, larger and more complex system-on-chips (SoCs) and disaggregated multi-chip systems are rapidly gaining popularity in the market, and data transmission within and between silicon components has become increasingly challenging, affecting power, performance and area (PPA).

On June 27, South Korean media Business Korea reported on June 24 that Samsung Electronics' semiconductor packaging industry has made significant progress and will lead TSMC in the field of panel-level packaging (PLP).

The artificial intelligence (AI) revolution is changing the way we design and manufacture everything from data centers to servers and chips. Chip technology is also shifting from traditional analog circuit integration to using multiple chips or chiplets in a single package.

XP Power officially announced on June 19th the launch of a new compact 550W AC-DC power supply that can be used for natural convection cooling, conduction cooling, and forced air cooling. This new PSU can meet medical and industrial applications and is suitable for a wide range of applications - including sealed enclosure environments.

On June 20, IT Home quoted Nikkei Asia as saying that TSMC is studying a new advanced chip packaging method that uses rectangular substrates instead of traditional round wafers to place more chips on each wafer.

ASML delivered the world's first High NA EUV extreme ultraviolet lithography machine to Intel at the end of last year. At the same time, it is researching a more powerful Hyper NA EUV lithography machine, which is expected to advance the semiconductor process to about 0.2nm, or 2 angstroms. The aperture value of ASML's first-generation Low NA EUV lithography machine is only 0.33, and the corresponding product is named NXE series, including the existing 3400B/C, 3600D, 3800E, and the future 4000F, 4200G, and 4X00.

On June 18, according to the Korea Economic Daily, Samsung Electronics will launch SAINT-D technology within this year, which can integrate HBM memory with processor chips in 3D. SAINT-D is a 3DIC advanced packaging technology of Samsung Electronics, which aims to vertically integrate logic die and DRAM memory die. The specific implementation of this technology is reported to be establishing a silicon interposer between the processor and the HBM chip.