Cadence Design Systems now offers Cadence Cerebrus Intelligent Chip Explorer, Cerebrus combined with Cadence RTL-to-Signoff processes, Provides advanced chip designers, CAD teams, and IP developers with the ability to increase engineering productivity by a factor of 10 (compared to manual methods) while achieving up to 20% better power, performance, and area. This is a new ML-based tool that automates and extends digital chip design, enabling customers to efficiently deliver demanding chip design goals.
As Cerebrus joins a broader portfolio of digital products, the company offers the industry's most advanced digital process that supports ML, from integration to implementation and validation. The new tools support the cloud and leverage the highly scalable computing resources provided by leading cloud providers to quickly meet the design needs of a wide range of markets, including consumer, superscale computing, 5G communications, automotive and mobile.
Dr Chen-chi Teng, senior vice president and general manager of Cadence Digital and Signoff Group, said: "Previously, design teams did not have an automated way to reuse historical design knowledge, which resulted in extra time spent on manual relearning for each new project. , and thus lost profits.” “The delivery of Cerebrus marks a revolution in the EDA industry, with ML-driven digital chip designs based on ML-driven digital chip designs, engineering teams have a greater opportunity to provide higher impact in their organizations, Because they can move away from manual processes. As the industry continues to move toward advanced nodes, and the scale and complexity of designs increase, Cerebrus allows designers to more effectively achieve PPA goals.”
“To effectively maximize the performance of new products using emerging process nodes, the digital implementation process used by our engineering teams needs to be constantly updated. Automated design process optimization is key to enabling higher-volume product development. With its innovative ML capabilities Together with the Cadence rtl-to-off tool, Cerebrus provides automated process optimization and floorplan exploration, improving design performance by more than 10%. Following this success, we will use this new approach in the development of our latest design projects." said Satoshi Shibatani, director of the Digital Design Technology Division, Renesas Shared R&D EDA Division.
"As Samsung foundry continues to deploy the latest process nodes, the efficiency of our Design Technology Collaborative Optimization (DTCO) program is important and we are always looking for innovative ways to outperform PPA in chip implementation. As part of our long-term partnership with Cadence, Samsung Foundry uses Cerebrus and Cadence digital implementation processes in multiple applications. We observed power reductions of more than 8 percent in some of our most critical modules in just a few days that would have taken months to work manually. In addition, we are using Cerebrus for automatic layout planning power distribution network sizing, which has reduced the final design time by more than 50%. Since Cerebrus and the digital implementation process provide better PPA and significant productivity improvements, the solution has become a valuable complement to our DTCO program, "said Sangyun Kim, Vice President of Contract Design Technology, Samsung.
